Memory device including page buffers

Abstract

A memory device includes a memory cell array; bit lines including even and odd bit lines extending in a first direction and alternately disposed; cache latches including even cache latches which exchange data with the memory cell array through the even bit lines and odd cache latches which exchange data with the memory cell array through the odd bit lines; 2^k data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2^k input/output pins; and column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to an input/output pin to which it is allocated. A pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches.