The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Dec. 07, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Byungil Kim, Gimpo-si, KR;

Seokhwan Choi, Gwangju, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/20 (2013.01); G11C 19/28 (2013.01); G09G 3/3677 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01);
Abstract

Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.


Find Patent Forward Citations

Loading…