The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Dec. 07, 2017
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Jacob Jul Schroder, Lyngby, DK;

Nicolai Asbjorn Smitt, København, DK;

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/14 (2006.01); H04L 12/861 (2013.01); G06F 12/02 (2006.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 13/1694 (2013.01); G06F 12/0292 (2013.01); G06F 12/109 (2013.01); G06F 12/1433 (2013.01); G06F 13/1626 (2013.01); G06F 13/1673 (2013.01); H04L 49/90 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received at the plurality of ingress interfaces, a first pool of memory access tokens, and one or more integrated circuits that implement a memory controller. The memory access tokens correspond to respective memory units and are distinct within the first pool. The memory controller is configured to selectively assign at least one individual memory access token to the ingress interfaces to govern write access to the memory units. The ingress interfaces write packets to memory units identified by the corresponding assigned memory access tokens. The network controller is configured to reassign a first memory access token from a first ingress interface to a second ingress interface between consecutive write commands from the first ingress interface based on a write access scheme to access non-sequential memory units.


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