The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jul. 25, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

William McAvoy, Raleigh, NC (US);

Brian Stempel, Raleigh, NC (US);

Spencer Williams, Raleigh, NC (US);

Robert Douglas Clancy, Cary, NC (US);

Michael Scott McIlvaine, Raleigh, NC (US);

Thomas Philip Speier, Wake Forest, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/1045 (2016.01); G06F 12/0891 (2016.01); G06F 12/0895 (2016.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1045 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 12/1063 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/152 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/608 (2013.01); G06F 2212/683 (2013.01);
Abstract

A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.


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