Power aware hash function for cache memory mapping

Abstract

A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., 'on') and which are in a lower power consumption mode (e.g., 'off'.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.