The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Aug. 08, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sundeep Chadha, Austin, TX (US);

David A. Hrusecky, Cedar Park, TX (US);

Elizabeth A. McGlone, Rochester, MN (US);

George W. Rohrbaugh, III, Charlotte, VT (US);

Shih-Hsiung S. Tung, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0804 (2016.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01);
Abstract

Flush avoidance in a load store unit including launching a load instruction targeting an effective address; encountering a set predict hit and an effective-to-real address translator (ERAT) miss for the effective address, wherein the set predict hit comprises a cache address of a cache entry; sending a data valid message for the load instruction to an instruction sequencing unit; and verifying the data valid message, wherein verifying the data valid message comprises: tracking the cache entry during an ERAT update; and upon completion of the ERAT update, encountering an ERAT hit for the effective address in response to relaunching the load instruction.


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