The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jun. 18, 2014
Applicant:

Hitachi, Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Hiromichi Yamada, Tokyo, JP;

Tsutomu Yamada, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/16 (2006.01); G06F 11/18 (2006.01); G11C 11/4076 (2006.01); G11C 11/409 (2006.01); G11C 29/52 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1048 (2013.01); G06F 11/18 (2013.01); G06F 12/16 (2013.01); G11C 11/409 (2013.01); G11C 11/4076 (2013.01); G11C 29/52 (2013.01); G11C 29/702 (2013.01); G11C 29/74 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.


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