The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Oct. 31, 2012
Applicant:

Mobileye Vision Technologies Ltd., Jerusalem, IL;

Inventors:

Gil Israel Dogon, Jerusalem, IL;

Yosi Arbeli, Rishon Le-Zion, IL;

Yosef Kreinin, Jerusalem, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 9/30 (2018.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3893 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 17/16 (2013.01); H03H 17/06 (2013.01); G06F 15/8053 (2013.01);
Abstract

An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K' bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per lane, wherein J′ is less than N multiplied by K′.


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