The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Aug. 28, 2018
Applicant:

Board of Regents, the University of Texas System, Austin, TX (US);

Inventors:

Earl Swartzlander, Austin, TX (US);

Lauren Guckert, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/523 (2006.01); G06F 7/507 (2006.01); G06F 7/501 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 7/507 (2013.01); G06F 7/501 (2013.01); G06F 7/523 (2013.01); G11C 13/0021 (2013.01);
Abstract

Memristor-based multipliers using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based multipliers, such as shift-and-add multipliers, Booth multipliers and array multipliers, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of multipliers. Furthermore, by using MAD gates, memristor-based multipliers can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based multipliers using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.


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