The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2019
Filed:
May. 08, 2017
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Partho Tapan Chaudhuri, Nagpur, IN;
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G06F 11/267 (2006.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/3187 (2013.01); G01R 31/31723 (2013.01); G01R 31/31724 (2013.01); G01R 31/318536 (2013.01); G01R 31/318544 (2013.01); G01R 31/318558 (2013.01); G06F 11/267 (2013.01); G06F 11/27 (2013.01);
Abstract
An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.