The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Oct. 27, 2016
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Milind Sonawane, San Jose, CA (US);

Amit Sanghani, San Jose, CA (US);

Jonathon E. Colburn, Ben Lomond, CA (US);

Rajendra Kumar reddy.S, Bangalore, IN;

Bala Tarun Nelapatla, Santa Clara, CA (US);

Sailendra Chadalavda, Milpitas, CA (US);

Shantanu Sarangi, Saratoga, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/26 (2014.01); G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/2607 (2013.01); G01R 31/2803 (2013.01); G01R 31/2806 (2013.01); G01R 31/2834 (2013.01); G01R 31/31701 (2013.01); G01R 31/31707 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01); G06F 11/00 (2013.01);
Abstract

A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.


Find Patent Forward Citations

Loading…