The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jul. 02, 2015
Applicant:

Kionix, Inc., Ithaca, NY (US);

Inventors:

Scott G. Adams, Ithaca, NY (US);

Charles W. Blackmer, Ithaca, NY (US);

Assignee:

Kionix, Inc., Ithaca, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81C 1/00301 (2013.01); H01L 21/30604 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5329 (2013.01); B81B 2207/096 (2013.01); B81C 2201/013 (2013.01);
Abstract

Disclosed are systems, methods, and computer program products for electronic systems with through-substrate interconnects and mems device. An interconnect formed in a substrate having a first surface and a second surface, the interconnect includes: a bulk region; a via extending from the first surface to the second surface; an insulating structure extending through the first surface into the substrate and defining a closed loop around the via, wherein the insulating structure comprises a seam portion separated by at least one solid portion; and an insulating region extending from the insulating structure toward the second surface, the insulating region separating the via from the bulk region, wherein the insulating structure and insulating region collectively provide electrical isolation between the via and the bulk region.


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