The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Aug. 21, 2015
Renesas Electronics Corporation, Tokyo, JP;
Norikazu Motohashi, Tokyo, JP;
Tomohiro Nishiyama, Tokyo, JP;
Tadashi Shimizu, Tokyo, JP;
Shinji Nishizono, Tokyo, JP;
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Abstract
A plurality of semiconductor devices each including a semiconductor chip having a high-side MOSFET and a semiconductor chip having a low-side MOSFET are mounted on a wiring board (PB). The wiring board (PB) includes a power supply wiring WVto which a power supply potential is supplied and output wirings WD, WD, and WDelectrically connecting a low-side drain terminal of each of the plurality of semiconductor devices to a plurality of output terminals. A minimum value and a maximum value of a current path width in the power supply wiring WVare referred to as a first minimum width and a first maximum width, respectively, and a minimum value and a maximum value of a current path width in the output wirings WD, WD, and WDare referred to as a second minimum width and a second maximum width, respectively. When the first minimum width is smaller than the second minimum width, the first minimum width is larger than half of the second maximum width, and when the second minimum width is smaller than the first minimum width, the second minimum width is larger than half of the first maximum width.