The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Mar. 08, 2017
Applicant:

Credo Technology Group Limited, Grand Cayman, KY;

Inventors:

Lawrence Chi Fung Cheng, San Jose, CA (US);

Haihui Luo, San Jose, CA (US);

Assignee:

Credo Technology Group Limited, Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/21 (2006.01); H03F 3/193 (2006.01); H04L 25/03 (2006.01); H04L 27/01 (2006.01); H03F 3/45 (2006.01); H03G 5/28 (2006.01); H03H 11/26 (2006.01); H03H 15/02 (2006.01);
U.S. Cl.
CPC ...
H04L 27/01 (2013.01); H03F 3/193 (2013.01); H03F 3/211 (2013.01); H03F 3/45201 (2013.01); H03G 5/28 (2013.01); H04L 25/03044 (2013.01); H04L 25/03878 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45361 (2013.01); H03H 11/26 (2013.01); H03H 15/02 (2013.01); H04L 25/03031 (2013.01);
Abstract

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.


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