The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Sep. 18, 2017
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Amiad Dvir, Irvine, CA (US);
Mike Rolfe Ferrara, Petaluma, CA (US);
Vitaly Zborovski, Herzliya Pituah, IL;
Mario Caresosa, Irvine, CA (US);
Ryan Hirth, Petaluma, CA (US);
Assaf Naor, Herzliya Pituah, IL;
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Abstract
In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.