The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Apr. 20, 2018
Applicant:

Aura Semiconductor Pvt. Ltd, Bangalore, IN;

Inventors:

Arnold J D'Souza, Bangalore, IN;

Shyam Somayajula, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/32 (2006.01); H03F 3/21 (2006.01); H03F 1/02 (2006.01); H03M 1/38 (2006.01);
U.S. Cl.
CPC ...
H03F 1/32 (2013.01); H03F 1/02 (2013.01); H03F 1/0227 (2013.01); H03F 1/3211 (2013.01); H03F 3/21 (2013.01); H03F 3/45475 (2013.01); H03F 3/45937 (2013.01); H03F 2200/129 (2013.01); H03F 2200/331 (2013.01); H03F 2201/3215 (2013.01); H03F 2203/45522 (2013.01); H03F 2203/45528 (2013.01); H03F 2203/45594 (2013.01); H03M 1/38 (2013.01);
Abstract

A fully differential amplifier includes a first feedback resistance, a second feedback resistance, a first input resistance and a second input resistance. A first ratio of the first feedback resistance to the first input resistance is equalized with that of a reference ratio of a pair of reference resistances. Similarly a second ratio of the second feedback resistance to the second input resistance is also equalized with that of the reference ratio. Such equalization operations may be performed during a calibration phase prior to normal operation of the fully differential amplifier. Accordingly, when a common mode voltage present on each of the first output terminal and the second output terminal varies during normal operation, contribution of an erroneous differential signal component across the pair of differential output terminals is prevented.


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