The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Nov. 15, 2016
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Chao-Cheng Lin, Taichung, TW;

Chien-Kai Peng, Taipei, TW;

Chen-Cheng Lin, Nantou County, TW;

Chen-Hsun Du, Taipei, TW;

Chorng-Jye Huang, Hsinchu, TW;

Chun-Ming Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/028 (2006.01); H01L 31/18 (2006.01); H01L 31/0747 (2012.01);
U.S. Cl.
CPC ...
H01L 31/022433 (2013.01); H01L 31/028 (2013.01); H01L 31/022425 (2013.01); H01L 31/022466 (2013.01); H01L 31/0747 (2013.01); H01L 31/1804 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.


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