The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Feb. 02, 2018
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Qing Liu, Irvine, CA (US);

Akira Ito, Irvine, CA (US);

Shom Surendran Ponoth, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7824 (2013.01); H01L 21/31111 (2013.01); H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/0882 (2013.01); H01L 29/66681 (2013.01);
Abstract

Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.


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