The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Aug. 30, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Tsutomu Miyamae, Yokohama Kanagawa, JP;

Nariyuki Fukuda, Yokohama Kanagawa, JP;

Kazuhito Hosaka, Kawasaki Kanagawa, JP;

Takeshi Yamaguchi, Kamakura Kanagawa, JP;

Suguru Tahara, Yokohama Kanagawa, JP;

Isao Ooigawa, Kawasaki Kanagawa, JP;

Keitarou Mishima, Yokohama Kanagawa, JP;

Yuichiro Sanuki, Urayasu Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G01R 31/318536 (2013.01); G11C 29/44 (2013.01);
Abstract

According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.


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