The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Dec. 21, 2017
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Craig DeSimone, Dacula, GA (US);

Praveen Singh, Alphareatta, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4093 (2006.01); H04L 25/03 (2006.01); G06F 1/04 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 11/4072 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 1/04 (2013.01); G11C 5/04 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 11/4072 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H04L 25/03057 (2013.01);
Abstract

An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer circuit may generate one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of the decision feedback equalizer (DFE) are delayed.


Find Patent Forward Citations

Loading…