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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10311932 B1

PDFFull Text
Date of Patent:
Jun. 04, 2019

Filed:

Mar. 12, 2018

Magnetic memory device

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Nobuyuki Umetsu, Kawasaki Kanagawa, JP;

Tsuyoshi Kondo, Kawasaki Kanagawa, JP;

Yasuaki Ootera, Yokohama Kanagawa, JP;

Takuya Shimada, Kawasaki Kanagawa, JP;

Michael Arnaud Quinsat, Yokohama Kanagawa, JP;

Masaki Kado, Kamakura Kanagawa, JP;

Susumu Hashimoto, Nerima Tokyo, JP;

Shiho Nakamura, Fujisawa Kanagawa, JP;

Tomoya Sanuki, Suzuka Mie, JP;

Yoshihiro Ueda, Yokohama Kanagawa, JP;

Yuichi Ito, Yokkaichi Mie, JP;

Shinji Miyano, Yokohama Kanagawa, JP;

Hideaki Aochi, Yokkaichi Mie, JP;

Yasuhito Yoshimizu, Yokkaichi Mie, JP;

Assignee:

Toshiba Memory Corporation, Tokyo, JP;

Attorney:

Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Primary Examiner:

Hoai V Ho

Assistant Examiner:

Jay W Radke

Int. Cl.
CPC ...
G11C 19/08 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 23/528 (2006.01); H01F 10/32 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 19/0841 (2013.01); G11C 19/0866 (2013.01); H01L 23/528 (2013.01); H01L 27/222 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01F 10/3286 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01);
Abstract

According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.

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