The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Mar. 09, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Fumiyoshi Matsuoka, Kawasaki Kanagawa, JP;

Kosuke Hatsuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01F 10/32 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 11/161 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); H01F 10/3254 (2013.01); H01F 10/3286 (2013.01); H01L 27/228 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.


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