The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Sep. 30, 2014
Boe Technology Group Co., Ltd., Beijing, CN;
K-tronics (Su Zhou) Technology Co., Ltd., Suzhou, Jiangsu Province, CN;
Shuhuan Yu, Beijing, CN;
Xiao Zhang, Beijing, CN;
Lijie Zhang, Beijing, CN;
Xitong Ma, Beijing, CN;
Peng Cheng, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
K-TRONICS (SU ZHOU) TECHNOLOGY CO., LTD., Suzhou, Jiangsu Province, CN;
Abstract
There is provided an IC board and a display apparatus. Switching components () are added between the internal interfaces (J, J. . . Jn; j, j. . . jn) corresponding to the backend data processing chips (U; U) and the frontend data processing chip (U), or a switching component () is added between the internal interfaces (j, j. . . jn) corresponding to the backend data processing chip (U) and another backend data processing chip (U). The switching components () can ensure normal signal transmission between the backend data processing chips (U; U) and the frontend data processing chip (U) or between the backend data processing chips (U; U) when no external test signal is input into the internal interfaces, i.e., when the IC board operates normally; and interrupt the signal transmission between the backend data processing chips (U; U) and the frontend data processing chip (U) or between the backend data processing chips (U; U) when the internal interfaces j, j. . . jn are input with an external test signal such that the impedance of the signal transmission path in the backend data processing chips (U; U) during the external testing remains consistent to avoid abnormal transmission of the external test signals and the signals during normal operation.