The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Apr. 12, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jaime Bravo, Berkeley, CA (US);

Vikrant Chauhan, Cohoes, NY (US);

Piyush Pathak, Fremont, CA (US);

Shobhit Malik, San Jose, CA (US);

Uwe Paul Schroeder, Santa Cruz, CA (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); Y02P 90/265 (2015.11);
Abstract

Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.


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