The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Oct. 25, 2012
Nvidia Corporation, Santa Clara, CA (US);
Nick Barrow-Williams, San Francisco, CA (US);
Brian Fahs, Los Altos, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
James Leroy Deming, Madison, AL (US);
Timothy John Purcell, Provo, UT (US);
Lucien Dunning, Santa Clara, CA (US);
Mark Hairgrove, San Jose, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.