The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Oct. 10, 2011
Applicants:

William J. Earl, Boulder Creek, CA (US);

Kevin J. Kranzusch, Los Gatos, CA (US);

Satya Kiran Popuri, Santa Clara, CA (US);

Christopher W. Johnson, Saratoga, CA (US);

Inventors:

William J. Earl, Boulder Creek, CA (US);

Kevin J. Kranzusch, Los Gatos, CA (US);

Satya Kiran Popuri, Santa Clara, CA (US);

Christopher W. Johnson, Saratoga, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 9/44 (2018.01); G06F 9/46 (2006.01); G06F 13/00 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4555 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45579 (2013.01);
Abstract

An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.


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