The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Feb. 23, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Cédric Denis Robert Airaud, Paris, FR;

Max John Batley, Cambridge, GB;

Ian Michael Caulfield, Cambridge, GB;

Thomas Edward Roberts, Cambridge, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 12/0223 (2013.01); G06F 12/0646 (2013.01); G06F 12/0893 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/13 (2018.01);
Abstract

Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector.


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