Replacement physical layer (phy) for low-speed peripheral component interconnect (pci) express (pcie) systems

Abstract

A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.