The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Dec. 06, 2017
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Mohamed Elsayed, Austin, TX (US);

Scott D. Willingham, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/565 (2006.01); G05F 1/46 (2006.01); G05F 1/575 (2006.01); G05F 3/22 (2006.01); G05F 3/24 (2006.01); G05F 3/30 (2006.01);
U.S. Cl.
CPC ...
G05F 1/575 (2013.01); G05F 1/565 (2013.01);
Abstract

A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.


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