The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Sep. 26, 2017
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Yasuhiro Sudo, Chino, JP;

Katsuhiko Maki, Chino, JP;

Hideo Haneda, Matsumoto, JP;

Akio Tsutsumi, Chino, JP;

Takashi Kurashina, Matsumoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/087 (2006.01); G04F 10/00 (2006.01); H03L 7/18 (2006.01); H03L 7/23 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); G04F 10/005 (2013.01); H03L 7/18 (2013.01); H03L 7/23 (2013.01);
Abstract

A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal.


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