The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Nov. 17, 2018
Applicant:

Iq-analog Corporation, San Diego, CA (US);

Inventor:

Oscar Elisio Mattia, San Diego, CA (US);

Assignee:

IQ-Analog Corporation, San Diego, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03K 19/21 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 19/21 (2013.01); H03K 19/1733 (2013.01);
Abstract

Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.


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