The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2019
Filed:
Sep. 20, 2017
Qualcomm Incorporated, San Diego, CA (US);
Nitz Saputra, San Bruno, CA (US);
Sang Min Lee, San Diego, CA (US);
Dongwon Seo, San Diego, CA (US);
Vinay Kundur, San Diego, CA (US);
Behnam Sedighi, La Jolla, CA (US);
Honghao Ji, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.