The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Oct. 18, 2017
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Takeshi Kawabata, Osaka, JP;

Kiyomi Hagihara, Osaka, JP;

Satoshi Kanai, Osaka, JP;

Takashi Yui, Shiga, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 33/62 (2010.01); H01L 23/40 (2006.01); H01L 33/64 (2010.01); H01L 33/00 (2010.01); H05K 7/20 (2006.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 23/40 (2013.01); H01L 33/0095 (2013.01); H01L 33/64 (2013.01); H01L 33/644 (2013.01); H05K 7/20463 (2013.01); H01L 25/0753 (2013.01); H01L 2224/48091 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.


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