The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Sep. 26, 2014
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Chang Hoon Kim, Ansan-si, KR;

Sang Min Kim, Ansan-si, KR;

Chi Hyun In, Ansan-si, KR;

Hong Suk Cho, Ansan-si, KR;

Dae Seok Park, Ansan-si, KR;

Assignee:

SEOUL VIOSYS CO., LTD., Ansan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/24 (2010.01); H01L 33/38 (2010.01); H01L 33/62 (2010.01); H01L 33/40 (2010.01); H01L 33/36 (2010.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 33/38 (2013.01); H01L 24/14 (2013.01); H01L 33/62 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01);
Abstract

A light emitting diode (LED) chip can include: a first pattern region having one or more curved parts; and a second pattern region at least partially surrounding the first pattern region. The first pattern region can include a first conductive type nitride-based semiconductor layer, an active layer, a second conductive type nitride-based semiconductor layer, a top electrode layer, and a top bump layer stacked over a substrate, the second pattern region can include a first conductive type nitride-based semiconductor layer, a bottom electrode layer, and a bottom bump layer stacked over the substrate, and the first pattern region can include one or more protrusion patterns formed in the one or more curved part.


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