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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10304928 B1

PDFFull Text
Date of Patent:
May. 28, 2019

Filed:

May. 30, 2017

Semiconductor device and method of manufacturing semiconductor device

Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Takahiro Tamura, Matsumoto, JP;

Yuichi Onozawa, Matsumoto, JP;

Takashi Yoshimura, Matsumoto, JP;

Hiroshi Takishita, Matsumoto, JP;

Akio Yamano, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:

Thao P Le

Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 21/263 (2006.01); H01L 21/265 (2006.01); H01L 21/322 (2006.01); H01L 29/739 (2006.01); H01L 29/12 (2006.01); H01L 21/225 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01); H01L 29/32 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0834 (2013.01); H01L 21/2253 (2013.01); H01L 21/263 (2013.01); H01L 21/265 (2013.01); H01L 21/266 (2013.01); H01L 21/322 (2013.01); H01L 21/324 (2013.01); H01L 27/0664 (2013.01); H01L 29/1095 (2013.01); H01L 29/12 (2013.01); H01L 29/32 (2013.01); H01L 29/36 (2013.01); H01L 29/66136 (2013.01); H01L 29/739 (2013.01); H01L 29/7397 (2013.01); H01L 29/8613 (2013.01);
Abstract

Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.

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