The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Jan. 29, 2016
Applicant:

Kaneka Corporation, Osaka-shi, Osaka, JP;

Inventors:

Hidemaro Saiki, Misawa, JP;

Akira Nishikawa, Kamikita-gun, JP;

Assignee:

KANEKA CORPORATION, Osaka-shi, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/52 (2006.01); F21V 29/83 (2015.01); H01L 27/32 (2006.01); F21V 19/00 (2006.01); F21V 23/00 (2015.01); F21S 2/00 (2016.01); F21S 8/00 (2006.01); F21V 15/01 (2006.01); F21Y 105/00 (2016.01); F21V 29/508 (2015.01); F21Y 115/15 (2016.01); F21Y 115/20 (2016.01);
U.S. Cl.
CPC ...
H01L 27/32 (2013.01); F21S 2/005 (2013.01); F21V 19/004 (2013.01); F21V 23/005 (2013.01); F21V 29/83 (2015.01); H01L 51/524 (2013.01); H01L 51/5221 (2013.01); F21S 8/03 (2013.01); F21V 15/01 (2013.01); F21V 23/001 (2013.01); F21V 29/508 (2015.01); F21Y 2105/00 (2013.01); F21Y 2115/15 (2016.08); F21Y 2115/20 (2016.08); H01L 51/529 (2013.01); H01L 51/5237 (2013.01); H01L 2251/5361 (2013.01);
Abstract

To provide, in a simple and cost-effective manner, a planar light-emitting module with reduced thickness as a whole, with its substrate end ensuring shock resistance and low risk of injury, and being excellent in transferring and dissipating heat. A light-emitting module of the present invention includes: a bezel having a leg part having an inner height H; a planar light-emitting tile; and a printed circuit board having a plurality of heat dissipating through holes. A heat dissipating interval is provided between the printed circuit board and the mounted surface. The printed circuit board includes a tile-side main surface being a soaking metal layer including through hole openings.


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