The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Feb. 25, 2016
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, Hubei, CN;

Inventors:

Chunqian Zhang, Guangdong, CN;

Chao Wang, Guangdong, CN;

Jingfeng Xue, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/77 (2017.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 29/417 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/13454 (2013.01); G02F 1/136209 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 21/77 (2013.01); H01L 27/12 (2013.01); H01L 27/1262 (2013.01); H01L 29/41733 (2013.01); G02F 2001/13685 (2013.01);
Abstract

An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns. A first through hole and a second through hole are arranged on the array substrate. One of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole. The other one of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole and is insulated from the first shielding pattern. The present invention where the array substrate and the method of forming the array substrate are proposed is related to a top-gate design. The driving ability of the TFT driving circuit still improves without increasing the original processes and production costs.


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