The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Mar. 01, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Hiroshi Nakaki, Yokkaichi Mie, JP;

Yosuke Mitsuno, Yokkaichi Mie, JP;

Tatsuya Okamoto, Inabe Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 29/04 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01); H01L 21/768 (2006.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11568 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/265 (2006.01); H01L 29/167 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 29/04 (2013.01); H01L 29/1037 (2013.01); H01L 29/1095 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/28282 (2013.01); H01L 21/76843 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/167 (2013.01);
Abstract

A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.


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