The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Jun. 30, 2015
Applicant:

Aledia, Grenoble, FR;

Inventors:

Frédéric Mercier, Saint Nicolas de Macherin, FR;

Philipe Gilet, Teche, FR;

Xavier Hugon, Teche, FR;

Assignee:

Aledia, Grenoble, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 27/15 (2006.01); H01L 33/08 (2010.01); H01L 33/18 (2010.01); H01L 33/24 (2010.01); H05B 33/08 (2006.01); H01L 33/20 (2010.01); H01L 33/38 (2010.01); H01L 33/44 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 27/153 (2013.01); H01L 33/08 (2013.01); H01L 33/18 (2013.01); H01L 33/24 (2013.01); H05B 33/083 (2013.01); H01L 33/20 (2013.01); H01L 33/385 (2013.01); H01L 33/44 (2013.01); H01L 33/62 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73257 (2013.01);
Abstract

An optoelectronic device including a first integrated circuit that includes:—a substrate, having first and second opposite surfaces; and—groups of sets of light-emitting diodes resting on the first surface. The integrated circuit also includes:—in the substrate, first side elements for electrically insulating portions of the substrate around each set; and—for each group on the second surface, at least one first conductive contact, connected to the first terminal of the group, and one second conductive contact, connected to the second terminal of the group. The device includes a second integrated circuit containing:—third and fourth opposite surfaces; and—third conductive contacts, located on the third surface and electrically connected to the first and second conductive contacts. The first integrated circuit is attached onto the third surface of the second integrated circuit.


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