The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Nov. 16, 2015
Applicant:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Inventors:

Michihiro Inoue, Tsukuba, JP;

Shiro Hara, Tsukuba, JP;

Fumito Imura, Tsukuba, JP;

Arami Saruwatari, Tosu, JP;

Sommawan Khumpuang, Tsukuba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/677 (2006.01); H01L 21/673 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02 (2013.01); H01L 21/6734 (2013.01); H01L 21/6773 (2013.01); H01L 21/67736 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01);
Abstract

A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.


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