The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Sep. 11, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yeonkyu Choi, Seoul, KR;

Seungjun Shin, Incheon, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); G11C 16/32 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2245 (2013.01); G11C 2207/2254 (2013.01); G11C 2207/2281 (2013.01);
Abstract

A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.


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