The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Mar. 29, 2016
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Haruhiko Terada, Kanagawa, JP;

Yotaro Mori, Kanagawa, JP;

Makoto Kitagawa, Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0038 (2013.01); G11C 8/10 (2013.01); G11C 13/00 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0033 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01);
Abstract

A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.


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