The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Dec. 20, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Michael D. Pardeik, Rochester, MN (US);

Edgar R. Cordero, Round Rock, TX (US);

Arindam Raychaudhuri, Kodihalli, IN;

Diyanesh B. Chinnakkonda Vidyapoornachary, Bangalore, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/406 (2006.01); G06F 1/3234 (2019.01); G06F 13/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G06F 1/3275 (2013.01); G11C 11/406 (2013.01); G06F 13/18 (2013.01); G11C 2207/2227 (2013.01); G11C 2211/4065 (2013.01); G11C 2211/4067 (2013.01);
Abstract

A method, system and memory controller are provided for implementing refresh power optimization during long idle mode in a memory subsystem utilizing Dynamic Random Access Memory (DRAM). The DRAM includes DRAM cells requiring periodic refresh. A DRAM activity monitoring mechanism monitors an instruction queue and asserts a predefined mode register bit when the instruction queue is empty. Responsive to the asserted predefined mode register bit, a refresh rate is increased and a low power mode is established by reducing DRAM core power level for optimizing refresh power during the long idle mode to provide enhanced system performance.


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