The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2019
Filed:
Apr. 13, 2017
Applicant:
Chengdu Haicun Ip Technology Llc, ChengDu, CN;
Inventor:
Guobiao Zhang, Corvallis, OR (US);
Assignees:
ChengDu HaiCun IP Technology LLC, ChengDu, SiChuan, CN;
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 13/00 (2006.01); H01L 27/06 (2006.01); H01L 45/00 (2006.01); H01L 27/102 (2006.01); H01L 27/112 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 13/0023 (2013.01); H01L 27/0688 (2013.01); H01L 27/1021 (2013.01); H01L 27/1128 (2013.01); H01L 27/11213 (2013.01); H01L 27/2436 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01);
Abstract
In a compact three-dimensional memory (3D-M), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.