The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Nov. 06, 2015
Applicants:

Shehab Ahmed, Doha, QA;

Ahmed A. Elserougi, Doha, QA;

Ahmed M. Massoud, Doha, QA;

Ahmed Salah Morsy, College Station, TX (US);

Inventors:

Shehab Ahmed, Doha, QA;

Ahmed A. Elserougi, Doha, QA;

Ahmed M. Massoud, Doha, QA;

Ahmed Salah Morsy, College Station, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); H01M 10/44 (2006.01); G05F 1/67 (2006.01); H02J 1/10 (2006.01); H02J 3/38 (2006.01); H02J 1/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/67 (2013.01); H02J 1/00 (2013.01); H02J 1/10 (2013.01); H02J 3/38 (2013.01); H02J 3/385 (2013.01); H02J 2001/106 (2013.01); Y02E 10/58 (2013.01);
Abstract

Voltage balancing and extracted output power circuit topologies use maximum power point and maximum power point tracking to provide voltage balancing and voltage and current adjustment to optimize extracted output power for corresponding DC voltage source strings (). The topologies used to control power generation include one or more voltage balancing circuits and/or power system optimizer circuits () to reduce decreased power utilization and enable independent operating voltages of DC voltage source strings () to provide voltage balancing and to deliver a maximum power independent of the voltage and current of other DC voltage source strings (). The current flowing in each DC voltage source string is controlled by the duty ratio of the corresponding switch (). The circuit topologies can include a plurality of voltage balancing/power system optimizer circuits ().


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