The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Nov. 30, 2016
Applicant:

Stmicroelectronics (Alps) Sas, Grenoble, FR;

Inventor:

Alexandre Pons, Vizille, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); G05F 1/59 (2006.01); G05F 1/56 (2006.01); G05F 1/569 (2006.01); H01R 24/60 (2011.01); H02J 7/02 (2016.01); H02J 7/06 (2006.01); H03F 3/45 (2006.01); H01R 107/00 (2006.01); H02J 7/10 (2006.01);
U.S. Cl.
CPC ...
G05F 1/59 (2013.01); G05F 1/56 (2013.01); G05F 1/569 (2013.01); H01R 24/60 (2013.01); H02J 7/022 (2013.01); H02J 7/06 (2013.01); H03F 3/45071 (2013.01); H01R 2107/00 (2013.01); H02J 2007/10 (2013.01); H03F 2203/45521 (2013.01); H03F 2203/45641 (2013.01);
Abstract

A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.


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