The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Mar. 05, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Bruno Miguel Vaz, Sao Domingos de Rana, PT;

Christophe Erdmann, Ballsbridge, IE;

Bob W. Verbruggen, Saggart, IE;

John E. McGrath, Cahir, IE;

Ali Boumaalif, Cork, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1023 (2013.01); H03M 1/1033 (2013.01); H03M 1/12 (2013.01); H03K 19/17708 (2013.01); H03M 2201/639 (2013.01);
Abstract

An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.


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