The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Dec. 24, 2017
Applicant:

Xiamen Sanan Optoelectronics Technology Co., Ltd., Xiamen, CN;

Inventors:

Anhe He, Xiamen, CN;

Suhui Lin, Xiamen, CN;

Jiansen Zheng, Xiamen, CN;

Kangwei Peng, Xiamen, CN;

Xiaoxiong Lin, Xiamen, CN;

Chenke Hsu, Xiamen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/00 (2006.01); H01L 33/62 (2010.01); H01L 33/40 (2010.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 33/40 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/13006 (2013.01); H01L 2224/13011 (2013.01); H01L 2224/13016 (2013.01); H01L 2224/13017 (2013.01); H01L 2224/13018 (2013.01); H01L 2224/13019 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81805 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/37001 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A Flip-chip LED chip includes: a substrate; a first semiconductor layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer, which extends downward to the first semiconductor layer; a first metal layer over part of the first semiconductor layer; a second metal layer over part of the second semiconductor layer; an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, with opening structures over the first metal layer and the second metal layer respectively; an eutectic electrode structure over the insulating layer, including a first eutectic layer and a second eutectic layer at vertical direction, and a first-type electrode region and a second-type electrode region at horizontal direction. Poor packaging caused by high eutectic void content during eutectic bonding process can therefore be reduced.


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