The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Oct. 13, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventor:

Kazuatsu Ito, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/08 (2006.01); H01L 27/32 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/28 (2013.01); H01L 21/8234 (2013.01); H01L 21/823412 (2013.01); H01L 27/08 (2013.01); H01L 27/088 (2013.01); H01L 27/3262 (2013.01); H01L 29/045 (2013.01); H01L 29/247 (2013.01); H01L 29/423 (2013.01); H01L 29/42364 (2013.01); H01L 29/42372 (2013.01); H01L 29/49 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/786 (2013.01); H01L 29/7869 (2013.01); H01L 29/78645 (2013.01);
Abstract

A semiconductor device includes a first thin film transistor () on a substrate (), the first thin film transistor including: a sub-gate electrode (); a first insulating layer () covering the sub-gate electrode; a main gate electrode () formed on the first insulating layer; a second insulating layer () covering the main gate electrode; an oxide semiconductor layer () having a layered structure of a first layer (A) and a second layer (B), the second layer having a larger band gap than the first layer; a first source electrode (); and a first drain electrode (), wherein as seen from a direction normal to the substrate, the oxide semiconductor layer () includes: a gate opposing region () that overlaps the main gate electrode; a source contact region that is in contact with the first source electrode (); a drain contact region that is in contact with the first drain electrode; and an offset region () that is provided at least one of between the gate opposing region and the source contact region and between the gate opposing region and the drain contact region, wherein at least a portion of the offset region overlaps the sub-gate electrode () with the first insulating layer () and the second insulating layer () therebetween.


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