The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2019

Filed:

Jul. 13, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Seong Yeol Mun, Cohoes, NY (US);

Kwan-Yong Lim, Niskayuna, NY (US);

Kijik Lee, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66484 (2013.01); H01L 21/02068 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/7831 (2013.01);
Abstract

A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.


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